1lytics

Designing 4x4 Multiplier using Lua

What is an Multiplier

In digital electronics, a binary multiplier is an electronic circuit, used to multiply two binary numbers.

A 4x4 multiplier multiplies two 4-bit binary numbers and produces 8-bit result.

Gorgeous Karnaugh Versions with Lua Support

Note: Not all versions of Gorgeous Karnaugh software supports Lua scripting. Check you version features here.

Writing the Lua Script to Build Truth Table

It is very simple to create truth table for multiplier using Lua script:

-- Create vars and func in next order
-- most significant bit has max index
-- and positioned at left
-- A3, A2, A1, A0,
gkAddInputVar('A',4, 0, -1)
--                 B3, B2, B1, B0
gkAddInputVar('B',4, 0, -1)
-- Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0
gkAddFunction('Y',8, 0, -1)
MaxInput = gkGetMaxInputVector()
for InputVec = 0, MaxInput do
    -- get 4 bits starting from bit #4
    A  = gkGetBits( InputVec, 4, 4 )
    -- get 4 bits starting from bit #0 (rightmost)
    B  = gkGetBits( InputVec, 0, 4 )
    gkSetOutput(InputVec, A*B)
end


Sum-of-Products Minimized K-Maps

Product-of-Sums minimization results has too much complexity, therefore we will not show them here. Sum-of-Products Minimized K-Maps shown below:

4x4 Multiplier Minimized Y0 Output K-Map 4x4 Multiplier Minimized Y1 Output K-Map 4x4 Multiplier Minimized Y2 Output K-Map 4x4 Multiplier Minimized Y3 Output K-Map 4x4 Multiplier Minimized Y4 Output K-Map 4x4 Multiplier Minimized Y5 Output K-Map 4x4 Multiplier Minimized Y6 Output K-Map 4x4 Multiplier Minimized Y7 Output K-Map

Building the Logic Gate Diagrams

In the “Coverage sets” pane select the needed coverage set. Next, select the “Coverages” — “Open Schematic”. In the appeared dialog window select appropriate diagram generation options, and press “Ok” button. After this, you got the logic gate diagram.

Logic gate diagram for SoP:

Logic Gate Diagram for SoP Minimized 4x4 Multiplier

Checking Logic Gate Diagram in a Simulator

You can use “CEDAR Logic Simulator” program to check how your logic gate diagram works. For this, choose menu item “File” — “Save for CedarLogic” in the Gorgeous Schematic, save the “.CDL” file and open it in the “CEDAR Logic Simulator”.

Note: Not all versions of Gorgeous Karnaugh software supports export logic gate diagrams to CedarLogic. Check you version features here.

Gorgeous Karnaugh Versions

You can learn about Gorgeous Karnaugh features and compare diferences between Gorgeous Karnaugh versions on the Gorgeous Karnaugh features page.