1lytics

Designing 4-to-2 Priority Encoder

What is a priority encoder

In digital electronic an encoder is the logic device that converts 2N input signals to N-bit coded outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero of the most significant input bit

If two or more inputs are given at the same time, the input having the highest priority will take precedence. The output V indicates if the input is valid.

Priority encoders are often used to control interrupt requests by acting on the highest priority request.

Defining the truth table

Let define the truth table for 4 inputs and 2 outputs (and valid “v” output) priority encoder:

#TABLE: x1,x2,x3,x4 => y1,y2,v
0000 => 000
0001 => 001
0010 => 011
0011 => 011
0100 => 101
0101 => 101
0110 => 101
0111 => 101
1000 => 111
1001 => 111
1010 => 111
1011 => 111
1100 => 111
1101 => 111
1110 => 111
1111 => 111

Building the K-Maps

Launch Gorgeous Karnaugh and select “File” — “New” — “From truth table” menu item. In the dialog window that appears, enter the above truth table, then press “Ok” button. The truth table will be accepted and K-Maps will be built:

Priority encoder Y1 K-Map Priority encoder Y2 K-Map Priority encoder V-output K-Map

Minimizing the K-Maps

Let minimize the K-Maps for Product-of-Sums (by 0):

Minimized for PoS priority encoder Y1 K-Map Minimized for PoS priority encoder Y2 K-Map Minimized for PoS priority encoder V-output K-Map

and get the functions minimal form:

v = (x1|x2|x3|x4);
y1 = (x1|x2);
y2 = (x1|x3) (x1|!x2);

Let minimize the K-Maps for Sum-of-Products (by 1):

Minimized for SoP priority encoder Y1 K-Map Minimized for SoP priority encoder Y2 K-Map Minimized for SoP priority encoder V-output K-Map

and get the functions minimal form:

v = !x2 x3 | x2 | x4 | x1;
y1 = x2 | x1;
y2 = !x2 x3 | x1;

Building the Logic Gate Diagrams

In the “Coverage sets” pane select the needed coverage set. Next, select the “Coverages” — “Open Schematic”. In the appeared dialog window select appropriate diagram generation options, and press “Ok” button. After this, you got the logic gate diagram.

Logic gate diagrams for PoS and SoP:

Logic gate diagram for PoS minimized priority encoder Logic gate diagram for PoS minimized priority encoder

Checking Logic Gate Diagram in a Simulator

You can use “CEDAR Logic Simulator” program to check how your logic gate diagram works. For this, choose menu item “File” — “Save for CedarLogic” in the Gorgeous Schematic, save the “.CDL” file and open it in the “CEDAR Logic Simulator”.

Note: Not all versions of Gorgeous Karnaugh software supports export logic gate diagrams to CedarLogic. Check you version features here.

Gorgeous Karnaugh Versions

You can learn about Gorgeous Karnaugh features and compare diferences between Gorgeous Karnaugh versions on the Gorgeous Karnaugh features page.



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