1lytics

Designing 2-to-4 Decoder

What is a Decoder

In digital electronic a decoder is the logic device that converts N-bit coded input signals to 2N output signals. For each input combination only one output is in active “High” level.

Defining the Truth Table

Let define the truth table for 2 inputs and 4 outputs of the decoder:

#TABLE: x1,x2 => y1,y2,y3,y4
00 => 0001
01 => 0010
10 => 0100
11 => 1000

Building the K-Maps

Launch Gorgeous Karnaugh and select “File” — “New” — “From truth table” menu item. In the dialog window that appears, enter the above truth table, then press “Ok” button. The truth table will be accepted and K-Maps will be built:

2-to-4 decoder Y1 K-Map 2-to-4 decoder Y2 K-Map 2-to-4 decoder Y3 K-Map 2-to-4 decoder Y4 K-Map

Minimizing the K-Maps

Let minimize the K-Maps for Product-of-Sums (by 0):

Minimized for PoS 2-to-4 decoder Y1 K-Map Minimized for PoS 2-to-4 decoder Y2 K-Map Minimized for PoS 2-to-4 decoder Y3 K-Map Minimized for PoS 2-to-4 decoder Y4 K-Map

and get the functions minimal form:

y1 = (x1) (x2);
y2 = (x1) (!x2);
y3 = (x2) (!x1);
y4 = (!x2) (!x1);

Let minimize the K-Maps for Sum-of-Products (by 1):

Minimized for SoP 2-to-4 decoder Y1 K-Map Minimized for SoP 2-to-4 decoder Y2 K-Map Minimized for SoP 2-to-4 decoder Y3 K-Map Minimized for SoP 2-to-4 decoder Y4 K-Map

and get the functions minimal form:

y1 = x1 x2;
y2 = x1 !x2;
y3 = !x1 x2;
y4 = !x1 !x2;

Building the Logic Gate Diagrams

In the “Coverage sets” pane select the needed coverage set. Next, select the “Coverages” — “Open Schematic”. In the appeared dialog window select appropriate diagram generation options, and press “Ok” button. After this, you got the logic gate diagram.

Logic gate diagrams for PoS and SoP:

Logic gate diagram for PoS minimized 2-to-4 decoder Logic gate diagram for PoS minimized 2-to-4 decoder

Checking Logic Gate Diagram in a Simulator

You can use “CEDAR Logic Simulator” program to check how your logic gate diagram works. For this, choose menu item “File” — “Save for CedarLogic” in the Gorgeous Schematic, save the “.CDL” file and open it in the “CEDAR Logic Simulator”.

Note: Not all versions of Gorgeous Karnaugh software supports export logic gate diagrams to CedarLogic. Check you version features here.

Gorgeous Karnaugh Versions

You can learn about Gorgeous Karnaugh features and compare diferences between Gorgeous Karnaugh versions on the Gorgeous Karnaugh features page.