1lytics

Simple SR Latch Based on NAND Gates

Simple SR latch is the most fundamental latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.

While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.

SR Latch operation

Transition graph for SR-latch is shown on the next picture:

Transition graph for SR-latch

Excitation table for SR-latch:

S R Qt Qt' => Qt+1 Qt+1'
0 0  0  1  =>  0    1
0 0  1  0  =>  1    0
0 1  0  1  =>  0    1
0 1  1  0  =>  0    1
1 0  0  1  =>  1    0
1 0  1  0  =>  1    0
1 1  0  1  =>  -    -
1 1  1  0  =>  -    -

NAND SR Latch in Gorgeous Schematic X

Gate list for Gorgeous Schematic X:

GATE S':IN; D1:#1
GATE R':IN; D2:#2

GATE D1:NAND2; Q:#1, D2:#1
GATE D2:NAND2; Q':#1,D1:#2

GATE Q:OUT
GATE Q':OUT

Logic gate diagram for simple SR-latch based on NAND gates:

Logic gate diagram for SR-latch - NAND

See also